Home · Documentation; ihi; d – AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite. First release of V ARM contract references: LEC-PREV ARM AMBA Specification Licence AMBA AXI Protocol Specification. AMBA® AXI4 (Advanced eXtensible Interface 4) is the fourth generation of the AMBA interface specification from ARM®. Xilinx Vivado Design Suite and.

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AMBA AXI Protocol Specification

Performance, Area, and Power. The key features of the AXI4-Lite interfaces are:.

This bus has an address and data phase similar to AHB, but a much reduced, low complexity signal list for example no bursts. Ready for adoption by customers Standardized: Enables Xilinx to efficiently deliver enhanced native memory, external memory interface and memory controller solutions across all application domains.

Supports both memory mapped and streaming type interfaces Provides a unified interface on IP across aarm, video, embedded and DSP functions Is easy to use, with features like automatic pipeline instantiation to help you more easily hit a specific performance target Is equal to or better than prltocol solutions in key attributes, such as fMAX, LUT usage, latency, and bandwidth. Computer buses System on a chip.

We have detected your current browser version is not the latest one. Support for burst lengths up to beats Quality of Service signaling Support for multiple region interfaces AXI4-Lite AXI4-Lite is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components.


It is supported by ARM Limited with wide cross-industry participation. Xilinx users will enjoy a wide range of benefits with the transition to AXI4 as a common user interface for IP. The timing aspects and the voltage levels on the bus are not dictated by the specifications.

The AXI4-Stream protocol is designed for unidirectional data transfers from master to slave with greatly reduced signal routing. Interfaces are listed by their speed in the roughly ascending order, so the interface at the end of each section should be the fastest. An important aspect of a SoC is not only which components or blocks it houses, but also how they interconnect.

Tailor the interconnect to meet system goals: Technical and de facto standards for wired computer buses.

Key features of the protocol are: AXI4-Lite is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components.

A simple transaction on the AHB consists of an address phase and a subsequent data phase without wait states: Amab standard models and checkers for designers to use Interface-decoupled: Consolidates broad array of interfaces into one AXI4so users only need to know one specificagion of interfaces Makes integrating IP from different domains, as well as developing your own or 3rd party partner IP easier Saves design effort because AXI4 IP are already optimized for the highest performance, maximum throughput and lowest latency.


Since its inception, the scope of AMBA has, despite its name, gone far beyond microcontroller devices. All interface subsets use the same transfer protocol Fully specified: AMBA is protpcol solution for the blocks to interface with each other. AXI4 is open-ended to support future needs Additional benefits: The interconnect is decoupled from the interface Extendable: It includes the following enhancements:.

AXIthe third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features wrm make it suitable for high speed sub-micrometer interconnect:.

The AMBA specification defines an on-chip communications standard for designing high-performance embedded microcontrollers. The key features of the AXI4-Lite interfaces are: Forgot your username or password?

Supports single and multiple data streams using the same set of shared wires Supports multiple axl widths within the same interconnect Ideal for implementation in FPGAs.

AMBA AXI Protocol Specification

Please upgrade to a Xilinx. This page was last edited on 28 Novemberat Access to the orotocol device is controlled through a MUX non-tristatethereby admitting bus-access to one bus-master at a time. APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals.

It facilitates development of multi-processor designs with large numbers of controllers and peripherals with a bus architecture.